With the proliferation of wireless standards, future devices will need to support multiple air interfaces and modulation formats. Software-defined-radio (SDR) technology enables such functionality. It uses a reconfigurable hardware platform across multiple standards. Because of these capabilities, software-defined radio has been touted as the superior—although as of yet unattainable—solution for base stations. As field-programmable-gate-array (FPGA) technology and intellectual-property (IP) cores evolve, however, SDR is increasingly becoming a reality.

Software-defined radios require the support of multiple modulation formats or waveforms. To develop each of these waveforms, the designer must surrender significant design and debug time. He or she also must have expertise in waveform architecture, hardware, and software. Typically, the architecture will be split across a general-purpose processor (GPP), digital signal processor (DSP), and dedicated hardware (implemented in the field-programmable gate array).

Now, FPGAs can take on more of the computational tasks that are required in waveform implementations. Field-programmable gate arrays have associated tools that help the system designer quickly implement, simulate, and test each of his or her waveforms in the SDR system. These system-level tools are used to abstract the details of HDL coding into a higher-level, modular, block-architectural design. This step is aided by the ready availability of communications, DSP, and embedded-processor IP cores, which can be used in the functional design.

Lastly, the IP cores are integrated into the system-level tools. This integration, when combined with the interworking of the tools, allows the rapid handoff from the implementation phase to the simulation phase to the testing phase and back until the waveforms are complete. The rapid handoff therefore translates into a faster development cycle for the designer. Often, it decreases the time to final implementation by 50% or more.

Software-defined radio is the underlying technology behind the Joint Tactical Radio System (JTRS) initiative. This initiative focused on developing software-programmable radios that could enable seamless, real-time communication across the U.S. military services and with coalition forces and allies. The functionality and expandability of JTRS is built upon an open architecture framework, which is called the software communications architecture.

JTRS terminals must support the dynamic loading of any one of over 25 specified air interfaces or waveforms. Typically, those waveforms are more complex than the waveforms that are used in the civilian sector. FPGAs have the necessary processing power and flexibility to address such requirements. At the same time, they stay within the power budget allotted to the system.

With its increased flexibility and communications security, SDR also is well suited for applications outside of the military arena. Through a combination of in-the-field hardware and software reconfigurability, SDR technology must support multiple air interfaces and modulation formats—just as future wireless devices must support them. The ideal platform for implementing SDR consists of programmable logic in conjunction with state-of-the-art design software and a comprehensive portfolio of intellectual property. Low-cost, high-performance FPGAs are now delivering the capabilities that are required to cost effectively implement SDR applications. This article will describe an optimized FPGA-based SDR system.

FIGURE 1 illustrates the hardware partitioning of an SDR-based 3G base station. This type of base station can be reconfigured to support multiple standards. In order to reconfigure the entire system, however, an SDR base station would ideally perform all of the signal-processing tasks in the digital domain. Yet current-generation wideband data converters cannot support the processing bandwidth and dynamic range that are required across different wireless standards. As a result, the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) are usually operated at an intermediate frequency (IF). Separate wideband analog front ends are used for subsequent signal processing to the radio-frequency (RF) stages.

Digital IF extends the scope of the digital signal processing beyond the baseband domain and out to the antenna—to the RF domain. This approach increases the flexibility of the system while reducing manufacturing costs. Compared to traditional analog techniques, digital-frequency conversion provides greater flexibility and higher performance (in terms of attenuation and selectivity). FPGAs provide a highly flexible and integrated platform to implement computationally intensive, digital IF functions including digital up- and/or downconverters. At the same time, they reduce the risk involved in introducing new techniques, such as DPD, CFR, and smart antennas.

Often, data formatting is required between the baseband-processing elements and the upconverter. Such formatting can be seamlessly added at the front end of the upconverter (FIG. 2). This technique provides a fully customizable front end to the upconverter. It also allows for the channelization of high-bandwidth input data. Custom logic or a soft-core embedded processor, such as the Nios processor, can be used to control the interface between the upconverter and the baseband-processing element.

In digital upconversion, the input data is baseband filtered and interpolated before it is quadrature modulated with a tunable carrier frequency. To implement the interpolating-baseband, finite-impulse-response (FIR) filter, one must first make speed-area tradeoffs. Such tradeoffs will uncover the optimal fixed- or adaptive-filter architectures for a particular standard. In addition, numerically controlled oscillator cores can be used. These cores will generate a wide range of architectures with very high performance and spurious-free dynamic ranges in excess of 115 dB. Depending on the number of frequency assignments that must be supported, multiple digital upconverters can be easily instantiated in a programmable-logic device.

Crest factors also must be taken into account. Third-generation (3G) code-division multiple-access (CDMA)-based systems and multi-carrier systems, such as orthogonal frequency division multiplexing (OFDM), exhibit signals with high crest factors (peak-to-average ratios). Such signals drastically reduce the efficiency of the power amplifiers (PAs) that are used in the base stations.